The present invention relates to magnetic heads, and more particularly, this invention relates to a magnetic head having embedded chips each containing read and/or write elements.
Many modern electronic components are created by thin film wafer processing. One category of component created by thin film processing is the tape head. Another category is the disk head.
Most tape heads are currently built on wafers using thin film processes, similar to the wafers used for fabricating disk heads. However, the operating efficiency of disk heads and tape heads are inherently different. Disk recording/reading is very efficient, as the disk media is extremely flat and smooth, has a very thin magnetic layer, is in a sealed environment, and the heads are constructed to function with a particular media. Writing and reading tapes must address very different challenges. For example, the head must work with different tape brands, which can have different physical and magnetic properties. Furthermore, most tape is composed of magnetic particles, which are coated onto the tape surface. The resulting media can have variations in coating thickness and particle dispersion. This, coupled with spacing loss variations due to embedded wear particles and debris, requires that magnetic bits in tape must be much larger than bits in disk media for achieving an acceptable signal-to-noise ratio. Tape bits are typically of the order of 100 times wider and 3 times longer than bits recorded onto disks. Disk drive heads are designed to fly over smooth disk surfaces in a controlled manner at speeds approaching 30 to 40 meters per second. By contrast, tape stacking and other requirements limit tape drive operating speeds to approximately 3 to 6 meters per second. Thus, to achieve data rates commensurate with disk drives, high performance linear tape drives typically employ heads having multiple pairs of write-read heads that operate simultaneously. For example, two pairs provide twice the data rate of one pair, and Linear Tape Open (LTO) heads have eight pairs of read and write elements for each direction.
Often in tape head fabrication, head images are laid out on the wafer such that the heads cut from the wafer are the required length for insertion in a tape drive. However, for LTO heads for example, the active area of the head is approximately 7 mms long, whereas the tape supporting surface of the head must be 23 mm long. The remaining 16 mm are blank, i.e. devoid of devices.
A problem is that thin film wafers are of a standardized size, and thus, the number of individual dies which contain the read/write recording devices that can be cut from each wafer is limited. Increasing use of more complex wafer processes, coupled with the high cost of wafer substrates makes achieving the highest number of heads possible from a single wafer an important head design priority.
An approach to increasing the number of dies per wafer is to make each die no larger than the active area needed for each head, Thus, for example, three partial span images can fit in the space of one full span LTO image. The dies are fabricated into chips which are then inserted into a passive carrier constructed of similar substrate material. In this way, the tape is fully supported over the width of the head, but wafer costs are dramatically reduced. Partial span heads are conventionally fabricated such that the closure portion of the head is completely surrounded by the carrier. The entire structure, including head and carrier, are machined together to form a uniform tape bearing surface, which is planer or cylindrical and has no steps, discontinuities or corners. Thus, the carrier fully encompasses the original chip and the seam between the chip and carrier are not discontinuous. This approach generally mandates that the chip image be tall enough for mechanical processing as well as provide enough material for forming the contour. This takes away wafer space, resulting in fewer chips per wafer, etc.
A second method is to fabricate the partial span chip, i.e. lap it, etc., so that its tape bearing surface is completed prior to assembly. This otherwise finished chip is then attached to a beam such that the tape bearing surfaces of both chip and beam has minimal discontinuities. Also, the closure portion of the chip is aligned with an inner surface of the beam to eliminate any discontinuities along the edge of the tape bearing surface. The object of this method is to make the chip and beam form as closely as possible a single, regular surface, even though in general there will be steps at the chip edges. This approach allows short partial span images, so wafer utilization is good. However, a problem inherent in this method is that it is difficult to assemble the chip and beam with near-perfect alignment at the tape bearing surface. It is also more difficult to attach a cable since the contacts are now recessed from the side of the beam, and conventional cable bonding tooling does not easily reach into the recess. It would be desirable to create a partial span head in order to obtain a high utilization of useful circuitry per wafer, thereby minimizing fabrication costs and decreasing the cost per unit of magnetic heads. It would also be desirable to avoid having to provide the head contour after the chip is cut from the wafer, as required by current partial span heads, as this not only forces the use of a taller image for handling purposes, it also makes stripe and throat height control more difficult.